AND Gate: Difference between revisions

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===AND Gate===
#REDIRECT [[Fault_Tree_Diagrams_and_System_Analysis]]
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[[File:I10.1.gif|center]]
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In an AND gate, the output event occurs if all input events occur.  In system reliability terms, this implies that all components must fail (input) in order for the system to fail (output).  When using RBDs, the equivalent is a simple parallel configuration.
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====Example====
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Consider a system with two components,  <math>A</math>  and  <math>B</math> .  The system fails if both  <math>A</math>  and  <math>B</math>  fail.  Draw the fault tree and reliability block diagram for the system.  The next two figures show both the FTD and RBD representations.
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[[File:I10.2.gif]] [[File:I10.3.gif]]
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The reliability equation for either configuration is:
 
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::<math>{{R}_{System}}={{R}_{A}}+{{R}_{B}}-{{R}_{A}}\cdot {{R}_{B}}</math>

Latest revision as of 16:59, 25 June 2015

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